1. Field of the Invention
This invention relates to charge-coupled device technology and particularly to the structure and method for fabricating such devices as shift registers.
2. Description of the Prior Art
The charge-coupled device (CCD) has become an important component of semiconductor technology. The state of CCD technology has become significantly developed since it was first introduced to the semiconductor industry a number of years ago. Knowledge of the characteristics of operation of CCD's is well known and, except for minor modifications, the present state of the art is presented in the article, "Charge-Coupled Devices--An Overview", by Walter F. Kosonocky, presented at the 1974 Western Electronics Show and Convention Technical Papers, Vol. 18, September 10-13, 1974, pages 2/1-2/20. The principle circuit element used in CCD technology is the shift register which is capable of transferring electrically isolated packets of charge representing digital or analog data across or just under the surface of a semiconductor or other charge transport material. The detectability of the transferred charge packets is clearly limited by their effective size, a factor determined by the potentials used to operate the CCD and the surface area over which the potentials are effective. In recent years there has been a trend to use lower drive potentials in semiconductor devices to conserve power thus making the area of devices a significant factor. With the density of data bit positions on CCD devices expected to be on the order of 250,000, and greater, bits per semiconductor chip, area is an important design factor.
Several CCD structures have been proposed previously which utilize anisotropic etching of silicon substrates to provide semiconductor structures which include non-planar surfaces. A general description of anisotropic etching is provided in the article, "Anisotropic Etching of Silicon", by Kenneth E. Bean, IEEE Transactions on Electron Devices, Vol. ED-25, No. 10, October 1978, pp. 1185-1193. Basically, anisotropic etching provides a technique in which etching is effected preferentially along certain crystalographic planes in a crystalline substrate and can be used to provide self-limiting V-grooves in the surface of a silicon substrate. For example, if a silicon crystal is cut into wafers having a major surface parallel to the (100) plane, anisotropic etching can provide a V-groove in the surface of the wafer in which the sides of the groove are at an angle corresponding to the (111) planes. Anisotropic etching has been previously described as a useful technique for reducing the effective area of CCD shift registers. The article, "V-Grooved Charge-Coupled Device", by K. K. Liu, IBM Technical Disclosure Bulletin, Vol. 20, No. 10, March 1978, page 3851, describes a two-phase CCD shift register in which the storage electrodes are partially formed within anisotropically etched V-grooves in the surface of a semiconductor substrate. The packets of charge in such a structure are transferred between adjacent V-grooves by a transfer electrode placed on the planar surface of the substrate, as in a conventional CCD shift register. The article, "V-Groove Charge-Coupled Device", by D. M. Kenney, IBM Technical Disclosure Bulletin, Vol. 21, No. 8, January 1979, page 3110, describes another technique for reducing surface area of a CCD shift register in which two CCD electrodes are placed in a single anisotropically etched recess. Other applications of V-groove structures to provide an increase in density of semiconductor components is described in the article, "Capacitor for Single FET Memory Cell", by G. V. Clarke and J. E. Tomko, IBM Technical Disclosure Bulletin, Vol. 17, No. 9, February 1975, pages 2579-80. This article describes the use of a V-groove to form part of a MOS capacitor for a single FET memory cell in order to reduce the surface area occupied by each memory cell. U.S. Pat. No. 4,070,690 to Wickstrom is of interest as it uses a U-shaped recess in a multilayer semiconductor substrate to provide vertical MOS transistors in which conductive electrodes are provided parallel to the longitudinal extent of the recesses. U.S. Pat. No. 4,126,881 to Basse et al is also of interest as it teaches the formation of a plurality of single FET memory cells in a single anisotropically etched V-groove in which a plurality of independently selectable access lines pass perpendicularly across each V-groove.